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Dwarkesh Podcast 2026-10-22-1

What will computer chips look like in 2045?

Intel's Ranade says process technology is within a few percent of TSMC, and the gap that matters is scale and on-time ramps. ASML builds fewer than 100 EUV machines a year, leading-edge output could reach about 2x with existing tool supply rather than 10x, and a tool ordered today lands in 2028. That timeline means 2030 supply is largely being decided by orders placed now, which is the constraint the Empires of AI piece and the CME contracts both sit on top of.

Dwarkesh Podcast 2026-05-28-1

Reiner Pope on Chip Design from the Bottom Up: Data Movement Dominates Arithmetic 7-to-1, B300's FP4-FP8 Gap as First Crack in NVIDIA's FLOPS Marketing, Splittable Systolic Arrays as Maddox's Architectural Wedge

NVIDIA's B300 datasheet ships FP4 at 3x FP8 speed where precision-scaling theory says 4x — the first public number that doesn't square with marketed FLOPS as a benchmark. The durable accelerator moat is array geometry plus memory hierarchy, not transistor budget: that's why Maddox, Majestic, Groq, and Cerebras all exist as funded alternatives, each architecture matched to a workload profile the general-purpose chip handles inefficiently. By 2027, enterprise procurement moves from NVIDIA versus not to which architectural bet fits the inference batch size.